The present invention relates to bus to bus interfaces in computer systems, and more particularly to improved arbitration control logic and method for arbitrating control of buses in a dual bus architecture computer system.
Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data is transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus controllers (i.e., devices which can control the computer system) and bus slaves (i.e., elements which are controlled by bus controllers).
Personal computer systems having more than one bus are known. Typically, a local bus is provided over which the CPU communicates with cache memory or a memory controller, and a system I/O bus is provided over which system bus devices such as the DMA controller, or the I/O devices, communicate with the system memory via the memory controller. The system I/O bus comprises a system bus and an I/O bus connected by a bus interface unit. The I/O devices communicate with one another over the I/O bus. The I/O devices are also typically required to communicate with system bus devices such as system memory. Such communications must travel over both the I/O bus and the system bus through the bus interface unit.
Often in computer systems it is necessary for expansion devices to arbitrate for ownership of the I/O bus of the computer system; i.e., to decide which expansion device may transfer information via the I/O bus. It is known to provide an arbiter which determines which expansion device may transfer information via the I/O bus, i.e., which allocates the bus. Such an arbiter serves as a central arbitration control point (CACP) via which all arbitration for the I/O bus occurs.
The I/O bus operates in time divided units which are called bus cycles. Bus cycles of the I/O bus are divided into arbitration cycles and grant cycles. During arbitration cycles, expansion devices compete for ownership of the I/O bus. During grant cycles, a device which has won ownership of the bus, transfers information.
I/O devices may only initiate memory read or write cycles to system memory during an arbiter grant mode. Such a method of serial arbitration imposes performance limitations on dual bus architecture computer systems due to the time required to separately perform arbitration and the memory read or write cycles which may occur only during an arbiter grant mode.
It is an object of the present invention, then, to provide an arbitration system and method for a dual bus computer architecture system which simultaneously permits (i) arbitration between a CPU and I/O devices contending for control of I/O bus and (ii) completion of an I/O controller device read or write operation to system memory or a CPU write operation to expansion memory on an I/O slave device.